1. Field of the Invention
The present invention generally relates to electrostatic discharge protection, and more particularly to a semiconductor element that is configurable as an electrostatic discharge protection power clamp or a potion of an output driver.
2. Description of the Prior Art
Electrostatic discharge (ESD) problems are extremely important in electronic circuits since it may only take one ESD strike to permanently damage an integrated circuit, making ESD protection a critical component of the integrated circuit design. ESD is generally a high-voltage transient with fast rise time and fast decay time. It basically requires a clamping device to limit the surge voltage to a safe level for the integrated circuit or components being protected.
FIG. 1 illustrates an ESD protection mechanism to alleviate an ESD current between a power rail VDD and a power rail VSS. As illustrated, ESD power clamp 20 can protect an output driver 10 formed by PMOS transistor MN0 and PMOS transistor MN0 from the damage caused by the ESD current between power rail s.
In general, ESD protection levels are determined by the composition of an ESD protection circuit, a layout for realizing the ESD protection circuit in an actual integrated circuit device, and a fabricating process used to fabricate the integrated circuit device. While ESD evaluation standards are the same irrespective of the type of integrated circuit device, the size of the integrated circuit device becomes increasingly small and the fabricating process becomes increasingly complicated as the degree of integration of the integrated circuit device becomes higher.
FIGS. 2-4 illustrate several possible ways of layout implementation of the above-mentioned circuit architecture.
With reference to FIG. 2, power rails VDD and VSS are placed between the P-type transistor array and the N-type transistor array and the power clamp is placed adjacent to P-type transistor array. Under such layout, since the power clamp occupies additional spaces, a whole size of the integrated circuit will be disadvantageously increased. Besides, as the power clamp is not close to the power rails VDD and VSS, the ESD current may directly strike the P-type transistor array and/or the N-type transistor array.
With reference to FIG. 3, the power rails VDD and VSS are not placed between the P-type transistor array and the N-type transistor array and the power clamp is between the power rails VDD and VSS. Under such layout, since the power rails VDD and VSS are not placed between the P-type transistor array and the N-type transistor array, the ESD current from power rails VDD to VSS will not be divided into half (compared to the layout of FIG. 2) such that the P-type transistor array and the N-type transistor array may be stroke by stronger ESD currents.
With reference to FIG. 4, the power rails VDD and VSS are placed between the P-type transistor array and the N-type transistor array and the power clamp is between the power rails VDD and VSS. Under such layout, since available space for the power clamp is limited, the effect of the ESD protection will be poor.
Accordingly, it is necessary to develop an ESD protection power clamp and layout implementation to effectively perform an ESD protection function in a small area.